1. Technical Field
Embodiments of the present invention relate to a data processing technology, and more particularly, to an analog-to-digital converter (ADC), which converts an analog signal to a digital signal, and an electronic system including the same.
2. Discussion of Related Art
An ADC having a flash architecture uses a relatively large amount of power consumption and has a relatively large area, which limits the implementation of the ADC on a system-on-chip (SoC).
An ADC having a folding architecture uses less power and has a smaller area. Such a folding ADC includes a switching block to invert a thermometer code during encoding.
False operations of the switching block during high-speed data conversation may generate an error code in the ADC, thereby reducing the overall performance of the ADC. Further, as the resolution of the data conversion operations performed by the folding ADC increases, the folding ADC needs an increasing number of switching elements, which results in an increase in the size the chip area and an increase in the amount of power used.
Thus, there is a need for an ADC that uses less power and takes up less area, which can reduce false operations based on switching operations and an electronic system including the same.